1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device having conductive layers, such as bit lines, which are closely formed to be parallel, and a method of fabricating the same.
2. Description of the Related Art
As the integration density of semiconductor memory devices, such as DRAMs, increases, more attention is being paid to methods of minimizing chip size. In recent years, DRAM cells having a design rule of 0.11 μm or less have been developed., However, as the design rule and chip size of DRAMs decrease, overcoming restrictions of photolithographic processes used to form the DRAMs and securing a sufficient process margin become more complicated.
Referring to FIG. 1, conventionally, an interlayer dielectric (ILD) 10 is formed on a substrate (not shown) on which a lower structure is formed. A bit line conductive layer 15 and a bit line capping layer 20 are formed on the ILD 10. To form the bit line conductive layer 15 and the bit line capping layer 20, a conductive material for a bit line and an insulating material for a bit line capping layer are sequentially stacked on the ILD 10 and then patterned using a photolithographic process. Next, spacers 25 are formed on the sidewalls of the bit line conductive layer 15 and the bit line capping layer 20. Thus, a bit line 30, which includes the bit line conductive layer 15, the bit line capping layer 20, and the spacers 25, is completed.
As the design rule is reduced, the critical dimension (CD) of the bit line becomes 100 nm or less. However, the foregoing conventional method using photolithographic exposure equipment cannot obtain finer bit line patterns. Thus, sufficiently reducing the cell size becomes difficult. Since the width of a bit line cannot be reduced, the misalignment margin between the bit line and a storage node contact hole to be formed later becomes very small. Also, the misalignment margin between a bit line and a bit line contact plug may be reduced, thus causing problems such as leakage.
Referring again to FIG. 1, a gap fill insulating layer 40 is formed to fill a gap between bit lines 30. However, as the gap between the bit lines 30 decreases with the reduced design rule, a void V frequently occurs in the gap fill insulating layer 40, as shown in FIG. 1. When the void V is filled with a conductive material for storage node contact plugs, a bridge phenomenon may occur between the storage node contact plugs.